/*
 * Copyright 2022 Rich yang, 18158898020@189.com
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied,
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */

`include "defines.v"

module ex_mem(
	input wire	clk,
	input wire	rst,
	input wire[5:0] stall,

	// source from execute info
	input wire[`RegAddrBus]		ex_wd,
	input wire			ex_wreg,
	input wire[`RegBus]		ex_wdata,

	input wire[`AluOpBus]		ex_aluop,
	input wire[`RegBus]		ex_mem_addr,
	input wire[`RegBus]		ex_reg2,

	// sink to mem info
	output reg[`RegAddrBus]		mem_wd,
	output reg			mem_wreg,
	output reg[`RegBus]		mem_wdata,

	output reg[`AluOpBus]		mem_aluop,
	output reg[`RegBus]		mem_mem_addr,
	output reg[`RegBus]		mem_reg2
);

	always @ (posedge clk) begin
		if (rst == `RstEnable) begin
			mem_wd	 <= `NOPRegAddr;
			mem_wreg <= `WriteDisable;
			mem_wdata <= `ZeroWord;
			mem_aluop <= `EXE_NOP_OP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2     <= `ZeroWord;
		end else if (stall[3] == `Stop && stall[4] == `NoStop) begin
			mem_wd	 <= `NOPRegAddr;
			mem_wreg <= `WriteDisable;
			mem_wdata <= `ZeroWord;
			mem_aluop <= `EXE_NOP_OP;
			mem_mem_addr <= `ZeroWord;
			mem_reg2     <= `ZeroWord;
		end else if (stall[3] == `NoStop) begin
			mem_wd	  <= ex_wd;
			mem_wreg  <= ex_wreg;
			mem_wdata <= ex_wdata;
			mem_aluop <= ex_aluop;
			mem_mem_addr <= ex_mem_addr;
			mem_reg2     <= ex_reg2;
		end
	end

endmodule
